Those look like memory-side caches per DDR5 interface, not L3 cache. Like on Apple M1 Pro.
The difference, if the placement clue is correct, is that MSC contains only values located in the associated DDR5. This eliminates a lot of coherency overhead, although it can also include directory information to track which L2 caches might hold values.
L3 is in each tile and in previous generations (Skylake/Ice Lake) it wasn't used as memory-side cache so there's no reason to think it will change. I wonder how SNC mode works with an odd number of columns though...
You could be right that L3 continues distributed sharing access to each fabric access point with a cores, just like earlier CPUs. That would be the conservative approach.
What caught my eye was what seems to be large blocks of SRAM associated with each of the 160b DDR5 interfaces. These four look like they add up to about 50 mm2 total. That would be around 60MB of SRAM at just over 10 bits per micron, which is an ordinary density for SRAM these days. Seems to match up with L3 size? Or maybe they have MSC and coherency directory structures in there, in addition to the classic caches.
Lucky if it is seen in 2024.
Those look like memory-side caches per DDR5 interface, not L3 cache. Like on Apple M1 Pro.
The difference, if the placement clue is correct, is that MSC contains only values located in the associated DDR5. This eliminates a lot of coherency overhead, although it can also include directory information to track which L2 caches might hold values.
L3 is in each tile and in previous generations (Skylake/Ice Lake) it wasn't used as memory-side cache so there's no reason to think it will change. I wonder how SNC mode works with an odd number of columns though...
SNC mode is not odd if you assume the chip is typically yielded at 32 usable cores.
You could be right that L3 continues distributed sharing access to each fabric access point with a cores, just like earlier CPUs. That would be the conservative approach.
What caught my eye was what seems to be large blocks of SRAM associated with each of the 160b DDR5 interfaces. These four look like they add up to about 50 mm2 total. That would be around 60MB of SRAM at just over 10 bits per micron, which is an ordinary density for SRAM these days. Seems to match up with L3 size? Or maybe they have MSC and coherency directory structures in there, in addition to the classic caches.