Monolithic Sapphire Rapids
Absolute Reticle Limit
At Intel Innovation 2022, Intel presented a wafer labelled “Raptor Lake-S, 34 core“, which Angstronomics immediately identified to be identical to the monolithic 34-core Sapphire Rapids MCC (Mid Core Count) design. Now that images have surfaced publicly, it’s time for us to share what we know about the largest die Intel has made to date.
Intel’s Largest Single Chip Ever
Using a handy image captured by David Altavilla, we can do some image processing to derive the die size of this massive chip. From our edited image, we find a die size around the 770 mm² mark. This makes it Intel’s largest die ever!
2010 Tukwila: 699 mm²
2016 Knights Landing: 683 mm²
2017 Skylake-XCC: 678 mm²
2023 Sapphire Rapids-MCC: 770 mm²
Core Count Regression
Sapphire Rapids introduces a much larger, faster CPU core combined with more IO and acceleration features such as AMX, which all consumes area. This results in a regression in core count for a given die size vs the previous generation. A 10nm wafer can fit 84 dies of 40-core Ice Lake, but only 68 dies of 34-core Sapphire Rapids. So, despite having fewer cores, the new generation takes 24% more wafers to fit the same number of chips. This gap widens once factoring a lower yield for larger chips.
Maximum Possible Die Size
Not only is it Intel’s largest die, it also is the absolute maximum die size possible for monolithic Sapphire Rapids. The die has a mesh layout of 7 columns and 9 rows including IO, flanked by the DDR5 interface. The die is already larger than 30 x 25mm. The lithography machine’s Reticle Limit has a maximum field exposure area of 33 x 26mm. This means it is literally impossible for Intel to add another row or column without exceeding the Reticle Limit.
As such, Intel has absolutely maximized core count for a monolithic design, using an odd number of mesh columns which they have not done before, and trading IO on the bottom row for 3 additional cores. Having 34 cores allows Intel some margin for binning this massive chip into 32-core parts to put on the market.
Chip Features
We have done an annotation showing the layout and key features of the 34-core chip.
34 Server Cores + Cache
(2x 512b + AMX, 2MB L2, 1.875MB L3 per core)
68MB L2 Total
63.75MB L3 Total
2 Accelerator Units
8 channel DDR5 (640-bit wide with ECC)
3 UPI 2.0 Links
80 Lanes PCIe Gen 5
8 Lanes DMI to Chipset
What About Chiplet Sapphire Rapids?
Intel’s chiplet strategy for Sapphire Rapids is not to disaggregate functions, but to break the reticle limit and give more silicon per chip. More silicon = More cores = More Performance at each power level. 60-core Sapphire Rapids stitches four 15-core dies with EMIB. From the wafer, we can see each die is about 390 mm², and there are 148 chips per wafer. This makes just 37 full processors per wafer. The full chip has:
60 Server Cores + Cache
(2x 512b + AMX, 2MB L2, 1.875MB L3 per core)
120MB L2 Total
112.5MB L3 Total
4 Accelerator Units
8 channel DDR5 (640-bit wide with ECC)
4 UPI 2.0 Links
112 Lanes PCIe Gen 5
8 Lanes DMI to Chipset
Cores Per Wafer
Doing some multiplication, this wafer has 2220 cores printed, while the monolithic design has 2312 cores on the wafer. The chiplet design has lower core density as the chip connection interface takes area as well. We measure that the EMIB connections contribute a whopping 20% of total die area. Meanwhile, current 40-core Ice Lake has 3360 cores on a wafer, 50% more.
Balancing Act
Intel has to balance area (cost) with core size, core count and amount of IO. The final piece in this balancing act is the performance, which we will see when the parts arrive in 2023.
Lucky if it is seen in 2024.
Those look like memory-side caches per DDR5 interface, not L3 cache. Like on Apple M1 Pro.
The difference, if the placement clue is correct, is that MSC contains only values located in the associated DDR5. This eliminates a lot of coherency overhead, although it can also include directory information to track which L2 caches might hold values.