You are so good. These YouTube leakers love inventing stuff and spreading it over 30 minutes, constantly guessing everything. Meanwhile the SKYGOD of Angstronomics is succinctly stating all the details without droning on and on.
A range of terrific advances, but the watershed item is MCM. As intel is discovering, managing coherency with cpu chiplets is not easy, & u better bet that massively higher bandwidth GPUs are a lot harder again.
If indeed AMD can glean the same advantages Zen did from chiplets w/ GPU, then Nvidia face the same bleak future than Intel are facing.
Monolithic certainly cannot compete at scale, & desktop GPUs are already constrained by die size effective limits.
Excellent article from the silicon god Skyjuice himself.. those areas looks impossibly small and if correct could result in incredible yields and perf/area metric.. wondering if amd have any significant improvements on ray tracing and media engines?
Wish AMD made a Navi30 with ~64WGP. At <400mm2, ~450W, $1500, that would have been easily possible and really put pressure on Nvidia. But perhaps wafer supply just wasn't there...
Ok, ready for the RDNA3 performance expectations now that we are getting tidbits like it might hit almost 4ghz. Can't wait for the claimed update on performance and power in the conclusion.
Your use of the word "legacy" in describing the CU count is questionable. RDNA 3 CU's have 128 FP32 ALU's, while prior to that, a CU had 64 FP32 ALU's.
Consider comparing a full Navi 21 GPU to a full Navi 31 GPU. If you describe the Navi 31 chip as having 96 "legacy CU's", one might consider it a relatively minor 20% upgrade over a full Navi 21 die with 80 CU's. The reality is that it's a 140% upgrade, as 96 RDNA 3 CU's have the same shading capacity as 192 RDNA 2 CU's.
All that said, it's still disappointing not to have any real details on what a RDNA 3 WGP or CU actually entails. Most important to me is to know whether the FP32 ALU count is a dedicated number, or if AMD took a page from nVidia's Ampere and turned the INT32 ALU into a mixed-function unit, which would raise the question of whether or not AMD's scheduling is better than nVidia's, which maxed out at about 40% of that additional FP32 capacity being realized in games at high resolution.
I question that MCD die size to cache / PHY ratio. A 32bit PHY in N21 is ~ 6mm and the 64MB cache die is ~ 36mm so that means 32MB cache + 64bit PHY would fit in around 30mm leaving 7.5mm left for the MCD <-> GCD connection (which I presume is some IF based connection).
Not impossible of course because a faster cache + beefier MCD <-> GCD link is possible but a bit of a curiosity.
Also the N32 spec does break the 1SE per 64bit PHY layout that N31 and N33 seem to have. I presume if this is true then there is no actual link there so a cut down 192bit based N32 part could still use 3 SE's with say 8WGPs enabled per SE.
You are so good. These YouTube leakers love inventing stuff and spreading it over 30 minutes, constantly guessing everything. Meanwhile the SKYGOD of Angstronomics is succinctly stating all the details without droning on and on.
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Greymon coping
I'm still here waiting for the 'performance and power' article. Teased at the end. Will it come before the Nov 3rd event?
A range of terrific advances, but the watershed item is MCM. As intel is discovering, managing coherency with cpu chiplets is not easy, & u better bet that massively higher bandwidth GPUs are a lot harder again.
If indeed AMD can glean the same advantages Zen did from chiplets w/ GPU, then Nvidia face the same bleak future than Intel are facing.
Monolithic certainly cannot compete at scale, & desktop GPUs are already constrained by die size effective limits.
Thank you fo the Great work
Excellent article from the silicon god Skyjuice himself.. those areas looks impossibly small and if correct could result in incredible yields and perf/area metric.. wondering if amd have any significant improvements on ray tracing and media engines?
AMD will officially reveal RDNA3 in less than 3 weeks, maybe it's time to leak the performance and power estimates???
Spot on. Thanks a lot.
Wish AMD made a Navi30 with ~64WGP. At <400mm2, ~450W, $1500, that would have been easily possible and really put pressure on Nvidia. But perhaps wafer supply just wasn't there...
Seems AMD is keeping actual performance specifics really tight lipped. Would think the teased next write-up on performance would be out by now if not.
A bit late but not that we've seen the cooler to a certain extent, this leak has gone up dramatically in validity. Good work here.
Ok, ready for the RDNA3 performance expectations now that we are getting tidbits like it might hit almost 4ghz. Can't wait for the claimed update on performance and power in the conclusion.
Your use of the word "legacy" in describing the CU count is questionable. RDNA 3 CU's have 128 FP32 ALU's, while prior to that, a CU had 64 FP32 ALU's.
Consider comparing a full Navi 21 GPU to a full Navi 31 GPU. If you describe the Navi 31 chip as having 96 "legacy CU's", one might consider it a relatively minor 20% upgrade over a full Navi 21 die with 80 CU's. The reality is that it's a 140% upgrade, as 96 RDNA 3 CU's have the same shading capacity as 192 RDNA 2 CU's.
All that said, it's still disappointing not to have any real details on what a RDNA 3 WGP or CU actually entails. Most important to me is to know whether the FP32 ALU count is a dedicated number, or if AMD took a page from nVidia's Ampere and turned the INT32 ALU into a mixed-function unit, which would raise the question of whether or not AMD's scheduling is better than nVidia's, which maxed out at about 40% of that additional FP32 capacity being realized in games at high resolution.
Great info. No BS.
Yeah straight up no bs like the YouTube leaks which change every week...keep up the solid work mate.
I question that MCD die size to cache / PHY ratio. A 32bit PHY in N21 is ~ 6mm and the 64MB cache die is ~ 36mm so that means 32MB cache + 64bit PHY would fit in around 30mm leaving 7.5mm left for the MCD <-> GCD connection (which I presume is some IF based connection).
Not impossible of course because a faster cache + beefier MCD <-> GCD link is possible but a bit of a curiosity.
Also the N32 spec does break the 1SE per 64bit PHY layout that N31 and N33 seem to have. I presume if this is true then there is no actual link there so a cut down 192bit based N32 part could still use 3 SE's with say 8WGPs enabled per SE.
It's 16MB of SRAM on the MCD according to this, plus another 16MB possible with 3D stacking.